Tray for semiconductor devices with castellations



FIG. 1 is a perspective view of a tray for semiconductor devices with castellations showing my new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevational view, the rear elevational view being a mirror image thereof;

FIG. 4 is a right side elevational view, the left side elevational view being a mirror image thereof; and,

FIG. 5 is a bottom plan view thereof.

The broken line showing of the environment is for illustrative purposes only and forms no part of the claimed design. 

The ornamental design for tray for semiconductor devices with castellations, as shown and described. 